1. Field of the Invention
The present invention relates to a semiconductor memory unit with a repair circuit.
2. Description of Related Art
FIG. 13 is a block diagram showing a configuration of a conventional semiconductor memory unit with a repair circuit. In FIG. 13, the reference numeral 41 designates an address comparator, 2 designates an address decoder, 4 designates a repair address memory, 6 designates a repair selection signal generator, 7 designates a memory cell array, 8 designates a repair memory cell array, and 42 designates a repair address decoder. The address comparator 41 includes an AND gate 411 and an inverter 413.
Next, the operation of the conventional semiconductor memory unit will be described.
The address decoder 2 decodes a read/write address signal 101 supplied from the outside. The read/write address signal 101 is a signal for determining the address of a read/write memory cell. On the other hand, the repair address decoder 42 always decodes a repair address signal 102 output from the repair address memory 4. The repair address signal 102 is a signal for indicating the address of a memory cell to be repaired.
Receiving the repair address signal 102 decoded by the repair address decoder 42 and the read/write address signal 101 decoded by the address decoder 2, the address comparator 41 compares them. In the course of this, the repair address memory 4 supplies the address comparator 41 with a repair activating signal 103 indicating the necessity of using the repair circuit. When the address the output signal of the address decoder 2 points agrees with the address the output signal of the repair address decoder 42 points, and when the repair activating signal 103 selects the use of the repair circuit, the address comparator 41 has the repair selection signal generator 6 supply the repair memory cell array 8 with a repair memory cell selection signal 108. The repair memory cell selection signal 108 is a signal for activating the repair memory cell corresponding to the selected address. In contrast, when the compared result indicates that the addresses disagree, or when the repair activating signal 103 indicates that the repair circuit is not to be used, the address comparator 41 supplies the memory cell selection signal 107 to the memory cell array 7. The memory cell selection signal 107 is a signal for activating the memory cell corresponding to the selected address.
With the foregoing configuration, the conventional semiconductor memory unit with a repair circuit has a problem of increasing the area of the unit because it must include the repair address decoder 42 besides the normal address decoder 2.